FIGS. 8(a) and 8(b) are cross-sectional views illustrating a field effect transistor (referred to as FET hereinafter) having a recess structure as an example of a conventional semiconductor device. In the figures, reference numeral 100 designates a GaAs semiconductor substrate having a surface, reference numeral 2 designates a GaAs buffer layer disposed on the surface of the GaAs semiconductor substrate 100, reference numeral 1 designates an n type GaAs active layer disposed on the surface of the buffer layer 2, reference numerals 15a and 15b designate recess structures, and reference numeral 4 designates a gate electrode comprising materials such as Al, of a width of 0.25 to 0.5 .mu.m, and disposed on the center of floors of the recess structures 15a and 15b. The distance from the edge of the gate electrode 4 to the corner of the recess structure 15a is about 0.5 .mu.m and the distance from the edge of the gate electrode 4 to the corner of the recess structure 15b is about 0.2 .mu.m. Reference numerals 3 and 10 designate a source electrode and a drain electrode, respectively, both comprising AuGe and related materials and disposed on both sides of the recess structures 15a and 15b. The distance between the source electrode 3 and the drain electrode 10 is 2.5 to 4 .mu.m. Reference numeral 6 designates a depletion region generated under the gate electrode 4.
FIGS. 9(a) to 9(d) are cross-sectional process views illustrating a fabricating method of a conventional FET, where the same reference numerals used in FIGS. 8(a) and 8(b) are to designate the same or corresponding parts. Reference numeral 18 designates a resist, and reference numeral 4a designates a layer comprising the gate electrode material.
The fabricating method will be described as follows. First, as shown in FIG. 9(a), the active layer 1 and the buffer layer 2 are successively grown on the surface of the semiconductor substrate 100 using an epitaxial growth method. Then, as shown in FIG. 9(b), the source electrode 3 and the drain electrode 10 are formed on the surface of the active layer using evaporation and lift-off method.
Next, the resist 18 having an opening between the source electrode 3 and the drain electrode 10 is formed covering the surfaces of the source electrode 3 and the drain electrode 10. Using this resist 18 as a mask, as shown in FIG. 9(d), the active layer 1 is etched to produce the recess structure 15a and furthermore, using the resist 18 as a mask, the gate electrode 4 is formed preferably by evaporation. Simultaneously with the production of the gate electrode 4, the layer 4a comprising the gate electrode material is also deposited on the resist 18.
Finally, the layer 4a comprising the gate electrode material on the resist 18 is removed together with the resist 18 to produce the FET shown in FIG. 8(a).
The operation of the FET will be described as follows. As can be seen in FIG. 8(a), the FET having the recess structure on the active layer 1 has the depletion region 6 under the gate electrode 4. This depletion region 6, when a negative voltage is applied to the gate electrode 4, grows horizontally mainly toward the drain electrode 10 as long as the depletion region 6 exists in the close proximity of the bottom of the recess structure 15a. The larger the ratio of this depletion region 6 to the path which describes the shortest distance connecting the gate electrode 4 and the drain electrode 10 within the active layer, the higher the gate-drain breakdown voltage becomes.
The conventional FET is constructed as described above. However, if the edge of the gate electrode 4 and the corner of the recess structure 15a are widely separated as shown in FIG. 8(a), the time for the FET to reach a stationary state after a voltage is applied becomes longer and characteristics such as a pulse response characteristic is thus degraded. For this reason, there are cases in which the distance between the edge of the gate electrode 4 and the corner of the recess structure 15b is shortened to improve the FET characteristics.
However, if the width of the recess structure 15b of the FET is reduced, as a negative voltage applied to the gate electrode 4 is increased, the depletion region 6 starts to grow out of proximity of the bottom of the recess structure 15b. It extends to an upper portion of the active layer 1 on which the drain electrode 10 is located, i.e., it extends upward along the wall of the recess structure 15b as shown in FIG. 8(b). Therefore, the ratio of the depletion region 6 to the path describing the shortest distance connecting the gate electrode 4 and the drain electrode 10 within the active layer 1 does not increase in accordance with an increase in the gate voltage, thereby decreasing the gate-drain breakdown voltage of the FET.
The structure of an FET designed to solve the above mentioned problem is shown in Japanese Published Utility Model Application No. Sho. 62-151769. FIG. 10 is a cross-sectional view illustrating a structure of another prior art FET which is similar to that of the FET shown in Japanese Published Utility Model Application No. Sho. 62-151769. In the figure, reference numeral 51 designates a semiconductor substrate, reference numeral 52 designates a buffer layer, reference numeral 53 designates an active layer, reference numeral 54 designates a source electrode, reference numeral 55 designates a drain electrode, reference numeral 56 designates a recess structure, reference numeral 57 designates a gate electrode, and reference numeral 58 designates a depletion region.
Furthermore, FIGS. 11(a) to 11(d) are cross-sectional views illustrating the fabricating method of the prior art FET, where the same reference numerals used in FIG. 10 designate the same or corresponding parts. Reference numeral 59 designates a resist.
The fabricating method of this prior art FET will be described as follows. First, as shown in FIG. 11(a), the buffer layer 52 and the active layer 53 are epitaxially grown in this order on the substrate 51, preferably by CVD. Next, a portion of the rear surface of the substrate 51 is etched to the proximity of the buffer layer 52 in a first etching step. Next, the source electrode 54 and the drain electrode 55 are formed on the active layer 53 by evaporation, a space separating these two electrodes corresponding to the portion of the substrate 51 which was etched away (FIG. 11(b)). Next, the resist 59 is deposited on the rear surface of the substrate 51 and a portion of the resist 59 where the gate electrode 57 is to be located is exposed to light only over a prescribed width and it is developed. Then, using this resist 59 as a mask, the rear surface of the substrate 51 is etched until the etching front reaches the active layer 53 in a second etching step using a phosphoric acid based etchant to produce the recess structure 56. Then, using the resist 59 as a mask, the gate electrode 57 is formed by evaporation of Al, and the resist 59 is removed together with the unnecessary Al layer 57 to produce the FET.
The operation of the FET will be described as follows. As shown in FIG. 10, this prior art FET has the depletion region 58 in the active layer 53 in contact with the gate electrode 57. This depletion region 58, when a negative voltage is applied to the gate electrode 57, grows horizontally mainly toward the drain electrode 55. However, in this FET, the drain electrode 55 is located on the surface of the active layer 53 opposite to the side having the recess structure 56. Therefore, even if the depletion region 58 grows out of the proximity of the bottom of the recess structure 56, it does not grow along the wall of the recess structure 56 like the conventional FET illustrated in FIG. 8(b), but it grows toward the surface of the active layer 53 on which the drain electrode 55 is located. Therefore, the ratio of the depletion region 58 to the path which describes the shortest distance connecting the gate electrode 57 and the drain electrode 55 within the active layer 53 increases in response to the voltage applied to the gate electrode 57. Even if the distance d between the corner of the recess structure 56 and the edge of the gate electrode 57 is quite small, i.e., about 0.2 .mu.m, the gate-drain breakdown voltage does not decrease.
As described above, in the prior art FET, the distance between the corner of the recess structure 56 and the edge of the gate electrode 57 is shortened and the gate-drain breakdown voltage does not decrease. However, since the recess structure 56 and the gate electrode 57 are located on the rear surface of the active layer 53, that is, on the side of the rear semiconductor substrate 51, in order to produce this structure, it is necessary to, after removing the portion of the semiconductor substrate 51 where the recess structure 56 is to be formed, deposit the resist 59 on the rear surface of the semiconductor substrate 51 and open an aperture for forming the recess structure 56 by an exposure to light followed by development of the resist 59 at a location corresponding to the recess formed by the first etching step. This opening is also used as a masking pattern when forming the gate electrode 57. However, since the width of the gate electrode is usually quite fine, i.e., 0.25 to 0.5 .mu.m, it is also necessary to make the width of the opening quite fine. Since the thickness of the semiconductor substrate 51 is usually several hundreds of microns, the depth of the recess formed on the semiconductor substrate 51 by the first etching step also becomes several hundreds of microns. If the resist 59 is deposited on a recess of such a depth, the resist 59 fills the recess and the thickness of the resist 59 in this recess becomes large. It is extremely difficult to perform a high precision exposure on a resist of such a large thickness, and the opening for forming the recess structure has poor precision. If this resist 59 is used to form the gate electrode 57, the gate length of the gate electrode 57 has poor precision and the position where the gate electrode is placed also has of poor precision. Since, in a transistor, the gate length is an important factor for determining transistor characteristics, in the prior art FET the desired transistor characteristics are not obtained and FETs of uniform characteristics are not obtained.
Furthermore, for the prior art FET, since the recess structure 56 is formed on the rear surface of the active layer 53, it is necessary to etch the active layer in the second etching step to produce the recess structure 56 after etching the portion of the semiconductor substrate 51 and the buffer layer 52. Therefore, the etching depth is large compared to the case where the active layer 53 alone is etched, so that this makes the etching precision poor and the desired recess width is not obtained. In a transistor, the recess width is also an important factor determining transistor characteristics and high precision is required. However, in the prior art FET, since the etching has poor precision and the desired recess width is not obtained, the desired transistor characteristics cannot be obtained and FETs of uniform characteristics cannot be obtained with great repeatability.